[AArch64] SME instructions with indexed operands do not have correct disassembly information #2285
Description
Working on the latest next branch, disassembling a range of SME instructions yields incorrect disassembly information, often with additional memory operands being defined.
It seems to be an issue with the pattern matching of [...]. A similar issue occurred when implementing PR #1907 and was fixed in PR #1925. I'm not sure how different the backend is now after the auto-sync update, but perhaps a similar fix can be implemented from this?
Listed below are some examples:
Issue - Operand 2 p3.s's index is identified as an additional memory operand.
cstool -d aarch64 67447125
0 67 44 71 25 psel p7, p1, p3.s[w13, 1]
ID: 735 (psel)
op_count: 4
operands[0].type: REG = p7
operands[0].access: WRITE
operands[1].type: REG = p1
operands[1].access: READ
operands[2].type: REG = p3
operands[2].access: READ
Vector Arrangement Specifier: 0x20
operands[3].type: MEM
operands[3].mem.base: REG = w13
operands[3].mem.disp: 0x1
Registers read: p1 p3 w13
Registers modified: p7
Groups: HasSVE2p1_or_HasSME
Issue - Operand p4 is mistaken for a memory operand and x10 as its register offset. Also, operands[0] should not have an access specifier, and operands[2] should not have a vector index
cstool -d aarch64 4131a2e0
0 41 31 a2 e0 st1w {za0h.s[w13, 1]}, p4, [x10, x2, lsl #2]
ID: 1047 (st1w)
op_count: 3
operands[0].type: SME_MATRIX
operands[0].sme.type: 2
operands[0].sme.tile: za0.s
operands[0].sme.slice_reg: w13
operands[0].sme.slice_offset: 1
operands[0].sme.is_vertical: false
operands[0].access: WRITE
Vector Arrangement Specifier: 0x20
Vector Index: 0
operands[1].type: MEM
operands[1].mem.base: REG = p4
operands[1].mem.index: REG = x10
operands[1].access: WRITE
Shift: type = 1, value = 2
Vector Index: 0
operands[2].type: MEM
operands[2].mem.base: REG = x2
operands[2].access: WRITE
Vector Index: 0
Registers read: p4 x10 x2
Groups: HasSME
Issue - Same as above.
cstool -d aarch64 c0089fe0
0 c0 08 9f e0 ld1w {za0h.s[w12, 0]}, p2/z, [x6]
ID: 434 (ld1w)
Is alias: 1354 (ld1w) with ALIAS operand set
op_count: 2
operands[0].type: SME_MATRIX
operands[0].sme.type: 2
operands[0].sme.tile: za0.s
operands[0].sme.slice_reg: w12
operands[0].sme.slice_offset: 0
operands[0].sme.is_vertical: false
operands[0].access: READ
Vector Arrangement Specifier: 0x20
Vector Index: 0
operands[1].type: MEM
operands[1].mem.base: REG = p2
operands[1].mem.index: REG = x6
operands[1].access: READ
Vector Index: 0
Registers read: p2 x6
Groups: HasSME