Arm, some main_v8 MVE instructions not disassembled #1897
Description
Instructions like
vldrw.u32 q1, [r1]
comes out as and ldc instruction. The decoding doesn't seem to recognise the fields that distinguish them.
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Instructions like
vldrw.u32 q1, [r1]
comes out as and ldc instruction. The decoding doesn't seem to recognise the fields that distinguish them.