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x64: convert movlhps #10898

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Merged
merged 6 commits into from
Jun 12, 2025
Merged

x64: convert movlhps #10898

merged 6 commits into from
Jun 12, 2025

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abrown
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@abrown abrown commented Jun 2, 2025

This change continues the push to convert all mov-related instruction and converts movlhps to use the new assembler (at least the SSE variant). In doing so, it discovers that we were incorrectly allowing an XmmMem as one of the operands; this is fixed to be Xmm only.

Comment on lines 141 to 144
;; movl %edx, %r10d
;; movq 0x40(%rdi), %r11
;; vmovsd (%r11, %r10), %xmm7
;; vmovlhps %xmm7, %xmm0, %xmm0
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Note how we're gaining an extra vmovsd here because we were probably doing some internal emit-time matching to emit vmovhps.

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It looks like movhps has the exact same encoding as movlhps, which might be how this worked beforehand? Nevertheless from an assembler point of view I'd much rather match the Intel manual for sure.

Perhaps though XmmMem could stay as an argument on some handwritten ISLE-helper and that delegates to movlhps and movhps as appropriate?

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Yeah, the more I stare at the manual, it could be that they are truly the same instruction and we should make that second operand an xmm_m64. I suspect that the names were different for some historical reason and we'll just have to paper over the mnemonic difference with #10918 once that is done.

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Ok, I ended up creating a separate instruction with the same encoding (avoids any customizations) and everything is fine. The only real user of vmovhps is Winch, though. I looked through the five uses of x64_movlhps in lower.isle and, unless I'm missing some auto-conversion somewhere, it appears to me that we are fine using the movlhps reg-to-reg form and don't really need movhps in Cranelift.

@@ -143,8 +143,8 @@
;; movq %rsp, %rbp
;; movl %edx, %r10d
;; movq 0x40(%rdi), %r11
;; movdqu (%r11, %r10), %xmm6
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The old version seems wrong... this should be a movsd I believe.

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Yeah definitely wrong, XmmMem auto-converted to Xmm always loads 128-bits, and this is just an incorrect translation and means that on-the-boundary-of-linear-memory loads of f32/f64 will be incorrectly identified as out-of-bounds.

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For this, mind adding this test to this PR?

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Added. It doesn't fail, though?

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(Maybe it would have failed with the old version?)

@github-actions github-actions bot added cranelift Issues related to the Cranelift code generator cranelift:area:x64 Issues related to x64 codegen labels Jun 2, 2025
abrown and others added 4 commits June 11, 2025 16:23
This change continues the push to convert all `mov`-related instruction
and converts `movlhps` to use the new assembler (at least the SSE
variant). In doing so, it discovers that we were incorrectly allowing an
`XmmMem` as one of the operands; this is fixed to be `Xmm` only.
Co-authored-by: Alex Crichton <alex@alexcrichton.com>
@abrown abrown marked this pull request as ready for review June 11, 2025 23:27
@abrown abrown requested review from a team as code owners June 11, 2025 23:27
@abrown abrown requested review from alexcrichton and removed request for a team June 11, 2025 23:27
@abrown abrown added this pull request to the merge queue Jun 12, 2025
@github-merge-queue github-merge-queue bot removed this pull request from the merge queue due to failed status checks Jun 12, 2025
@alexcrichton
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Failure is here and will need a new exception here

@github-actions github-actions bot added the winch Winch issues or pull requests label Jun 12, 2025
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@abrown abrown enabled auto-merge June 12, 2025 16:25
@abrown abrown added this pull request to the merge queue Jun 12, 2025
Merged via the queue into bytecodealliance:main with commit 1c6c765 Jun 12, 2025
160 checks passed
@abrown abrown deleted the asm-movlhps branch June 12, 2025 18:09
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