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bugIncorrect behavior in the current implementation that needs fixingIncorrect behavior in the current implementation that needs fixingcraneliftIssues related to the Cranelift code generatorIssues related to the Cranelift code generatorcranelift:area:riscv64Issues related to the RISC-V 64 backend.Issues related to the RISC-V 64 backend.
Description
.clif
Test Case
Please see the attachment for the complete case.
Environment
qemu-riscv64
to emulate execution on an x86 machine.
Description
When set opt_level = none
, it executes correctly.
%main() -> [-1377347706, 7919883821509745605, -0x1.891b7ep-1]
When set opt_level = speed
, it crashes with a Illegal instruction (exit code -4).
Here is an IR snippet from the main function.
block1:
v48 = stack_addr.i64 ss0
atomic_store.i32 little v6, v48
return v6, v41, v19
block5:
jump block4(v13, v20)
block6:
jump block4(v13, v3)
block7:
jump block4(v13, v10)
block3:
v40 = bitcast.i32x4 little v33
jump block4(v40, v20)
block4(v78: i32x4, v79: f64):
v42 = swizzle v11, v11
v43 = fcmp.f64 ugt v10, v20
v44 = avg_round v78, v78
jump block1
block8:
v21 = stack_addr.i64 ss1
v22 = load.i16x8 little v21+1
v23 = stack_addr.i64 ss0
v24 = load.f32x4 little v23+9
v25 = stack_load.f64x2 ss1
v26 = bitrev.i16 v5
v27 = fsub.f32 v9, v9
br_table v6, block9, [block11, block12, block14]
block11:
jump block10(v24, v12) ; v12 = const0
block12:
jump block10(v24, v22)
block14:
jump block15
With opt_level=speed
, I tried removing some dead code, such as v48
and the atomic_store
in block1, which makes the program execute correctly.
I also tried replacing all jumps to block14 with jumps to block15, which still results in correct execution of the test case.
I can't figure out the reason behind this illegal instruction.
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bugIncorrect behavior in the current implementation that needs fixingIncorrect behavior in the current implementation that needs fixingcraneliftIssues related to the Cranelift code generatorIssues related to the Cranelift code generatorcranelift:area:riscv64Issues related to the RISC-V 64 backend.Issues related to the RISC-V 64 backend.