opentitan: remove architecture reference from mainboard #191
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rjoleary
reviewed
Nov 18, 2019
rjoleary
previously approved these changes
Nov 18, 2019
we found in coreboot that maintaining a specific hierarchy of reference made life best. Currently we reference the architecture from both the mainboard and the cpu. That gets messy, we have learned. Reference the architecture from the cpu. Implement halt for the cpu and the soc. Use soc::halt in the mainboard code. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
rjoleary
approved these changes
Nov 18, 2019
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I'm working on tracing the CI failure you're seeing. Will update this patch when I'm further through the investigation. |
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That Rust pull request has been approved, so this issue might be fixed by the time this lands in nightly. I expect this to have some fall-out within the project, as you will no longer have access to any |
Centril
added a commit
to Centril/rust
that referenced
this pull request
Nov 20, 2019
… r=alexcrichton [RISCV] Disable Atomics on all Non-A RISC-V targets In a `TargetOptions` configuration, `max_atomic_width: None` causes `max_atomic_width()` to return `Some(target_pointer_width)`. So, contrary to assumptions, `max_atomic_width: None` means you do have atomic support! RISC-V's rv32i and rv32imc do not have architectural support for atomic memory accesses of any size, because they do not include the `A` architecture extension. This means the values in the target definition should be `Some(0)`. This bug has been observed via a build failure with oreboot/oreboot#191, where LLVM was still generating libcalls for atomic operations. According to rust-lang/compiler-builtins, "Rust only exposes atomic types on platforms that support them, and therefore does not need to fall back to software implementations." - so this PR tries to bring rustc inline with this decision. This commit also removes the outdated bug link, which references a now irrelevant GCC bug. I will likely also have to revisit the `min_atomic_width` of all the RISC-V targets so they are correct and match what the hardware is capable of (which is more restricted than one might imagine). r? @alexcrichton
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I did a rustup to 11/20 version and ... still doesn't work. But maybe it did not percolate through yet. |
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Yeah, sadly I cannot see what's in the 20 November 2019 nightly edition (and https://rust-lang.github.io/rustup-components-history/ does not tell you which commit each nightly was built from) |
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I downloaded today's nightly ( I've attached the build output, but I think the summary is it's all successful (except a few warnings). Build Output |
alistair23
previously approved these changes
Nov 22, 2019
rjoleary
previously approved these changes
Nov 24, 2019
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already done in another PR |
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we found in coreboot that maintaining a specific hierarchy of reference
made life best.
Currently we reference the architecture from both the mainboard and the
cpu. That gets messy, we have learned.
Reference the architecture from the cpu. Implement halt for the
cpu and the soc.
Use soc::halt in the mainboard code.