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BenAtIBMcrgeddes
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Update ATRMISS registers for Axone
The address changed and there are now two. Change-Id: Iad60f8ec843ed61d28ef11903d8258ecfe213aa3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72965 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72986 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
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‎src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C

Lines changed: 34 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
/* */
66
/* OpenPOWER HostBoot Project */
77
/* */
8-
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
8+
/* Contributors Listed Below - COPYRIGHT 2015,2019 */
99
/* [+] International Business Machines Corp. */
1010
/* */
1111
/* */
@@ -40,6 +40,8 @@
4040
#include <p9_nv_ref_clk_enable.H>
4141
#include <p9_misc_scom_addresses.H>
4242
#include <p9_misc_scom_addresses_fld.H>
43+
#include <p9a_misc_scom_addresses.H>
44+
#include <p9a_misc_scom_addresses_fld.H>
4345

4446
//------------------------------------------------------------------------------
4547
// Constant definitions
@@ -70,13 +72,19 @@ fapi2::ReturnCode p9_npu_scominit(
7072
fapi2::ReturnCode l_rc;
7173
fapi2::buffer<uint64_t> l_atrmiss = 0;
7274
fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR_Type l_npu_p9n_dd1;
75+
fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR_Type l_axone;
7376

7477
// read attribute to determine if P9N DD1 NPU addresses should be used
7578
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR,
7679
i_target,
7780
l_npu_p9n_dd1),
7881
"Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR)");
7982

83+
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR,
84+
i_target,
85+
l_axone),
86+
"Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR)");
87+
8088
// apply NPU SCOM inits from initfile
8189
FAPI_DBG("Invoking p9.npu.scom.initfile...");
8290
FAPI_EXEC_HWP(l_rc,
@@ -95,16 +103,31 @@ fapi2::ReturnCode p9_npu_scominit(
95103
l_atrmiss.setBit<PU_NPU_SM2_XTS_ATRMISS_FLAG_MAP>()
96104
.setBit<PU_NPU_SM2_XTS_ATRMISS_ENA>();
97105

98-
FAPI_TRY(fapi2::putScomUnderMask(i_target,
99-
((l_npu_p9n_dd1) ?
100-
(PU_NPU_SM2_XTS_ATRMISS) :
101-
(PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1)),
102-
l_atrmiss,
103-
l_atrmiss),
104-
"Error from putScomUnderMask (0x%08X)",
105-
((l_npu_p9n_dd1) ?
106-
(PU_NPU_SM2_XTS_ATRMISS) :
107-
(PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1)));
106+
if (!l_axone)
107+
{
108+
FAPI_TRY(fapi2::putScomUnderMask(i_target,
109+
((l_npu_p9n_dd1) ?
110+
(PU_NPU_SM2_XTS_ATRMISS) :
111+
(PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1)),
112+
l_atrmiss,
113+
l_atrmiss),
114+
"Error from putScomUnderMask (0x%08X)",
115+
((l_npu_p9n_dd1) ?
116+
(PU_NPU_SM2_XTS_ATRMISS) :
117+
(PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1)));
118+
}
119+
else
120+
{
121+
// Axone
122+
// P9A_PU_NPU2_NTL1_XTS_ATRMISS = 0x050112FA
123+
FAPI_TRY(fapi2::putScomUnderMask(i_target, P9A_PU_NPU2_NTL1_XTS_ATRMISS, l_atrmiss, l_atrmiss),
124+
"Error from putScomUnderMask (0x%08X)",
125+
P9A_PU_NPU2_NTL1_XTS_ATRMISS);
126+
// P9A__NTL1_XTS_ATRMISS = 0x050116FA
127+
FAPI_TRY(fapi2::putScomUnderMask(i_target, P9A__NTL1_XTS_ATRMISS, l_atrmiss, l_atrmiss),
128+
"Error from putScomUnderMask (0x%08X)",
129+
P9A__NTL1_XTS_ATRMISS);
130+
}
108131

109132
// enable NVLINK refclocks
110133
FAPI_DBG("Invoking p9_nv_ref_clk_enable...");

‎src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6503,6 +6503,23 @@
65036503
</chip>
65046504
</chipEcFeature>
65056505
</attribute>
6506+
<!-- ******************************************************************** -->
6507+
<attribute>
6508+
<id>ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR</id>
6509+
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
6510+
<description>
6511+
Axone only: Use the Axone register addresses for the PHY0 BAR registers, PHY1 BAR registers, and MMIO BAR registers
6512+
</description>
6513+
<chipEcFeature>
6514+
<chip>
6515+
<name>ENUM_ATTR_NAME_AXONE</name>
6516+
<ec>
6517+
<value>0x10</value>
6518+
<test>GREATER_THAN_OR_EQUAL</test>
6519+
</ec>
6520+
</chip>
6521+
</chipEcFeature>
6522+
</attribute>
65066523
<!-- ********************************************************************* -->
65076524
<attribute>
65086525
<id>ATTR_CHIP_EC_FEATURE_SKEWADJ_P9NDD1_INIT</id>

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