library ieee;
use ieee.std_logic_1164.all;

entity Foo is
    generic (
        type DATA_TYPE;
        type DATA_ARRAY_TYPE is array (natural range <>) of data_type;
        INPUTS : positive);
    port (
        selector : in std_ulogic_vector(INPUTS-1 downto 0);
        input : in data_array_type(0 to INPUTS-1);
        output : out data_type);
end entity;

architecture rtl of Foo is

begin

end architecture;

library ieee;
use ieee.std_logic_1164.all;

library std;
use std.env.all;

entity Bar is
end entity;

architecture rtl of Bar is

    constant INPUTS : positive := 3;

    subtype data_type is std_ulogic_vector(7 downto 0);
    type data_array_type is array (0 to INPUTS - 1) of data_type;

    signal selector : std_ulogic_vector(INPUTS - 1 downto 0) := (others => '0');
    signal input : data_array_type := (others => (others => '0'));
    signal output : data_type;

begin

    foo_inst : entity work.Foo
        generic map (
            DATA_TYPE => data_type,
            DATA_ARRAY_TYPE => data_array_type,
            INPUTS => INPUTS)
        port map (
            selector => selector,
            input(0) => input(0),
            input(1) => input(1),
            input(2) => input(2),
            output => output);

end architecture;