Error: unexpected ) while parsing range, expecting one of (, **, to or downto #1245
Description
Hi, I have the following pattern in my codebase. I think it's valid VHDL, since GHDL and Vivado can handle it.
library ieee;
context ieee.ieee_std_context;
entity reproducer is
end entity;
architecture rtl of reproducer is
type std_logic_array is array (natural range <>) of std_logic_vector;
function test(data_in : in std_logic_array) return std_logic_vector is
variable data_out : data_in(data_in'low)'subtype := (others => '0');
begin
data_out := data_in(0);
return data_out;
end function test;
begin
end architecture;When analyzing with nvc (nvc --std=2008 -a ../reproducer.vhd), I get:
** Error: type mark DATA_IN does not denote a type or a subtype
> ../reproducer.vhd:12
|
12 | variable data_out : data_in(data_in'low)'subtype := (others => '0');
| ^^^^^^^ DATA_IN is a constant name
** Error: unexpected ) while parsing range, expecting one of (, **, to or downto
> ../reproducer.vhd:12
|
12 | variable data_out : data_in(data_in'low)'subtype := (others => '0');
| ^ this token was unexpected