VHDL 2008 - conditional_force_assignment is parsed as a simple_force_assignment causing error

The following signal assignment statement tries to be parsed as a simple force assignment, instead of conditional force assignment

```
process(all)begin 
  a <= force '1' when g_force else '0';
end process;
```


```
simple_force_assignment ::=
 target <= force [ force_mode ] expression ;
```

```
conditional_force_assignment ::=
 target <= force [ force_mode ] expression when condition ..
```