Unexpected behaviour when using stable attribute #1177
Description
Running the example below I see that the stable attribute in VHDL gives a different result in NVC compared to GHDL and Modelsim. In GHDL and Modelsim the behaviour is as expected, triggering the assert after a runtime of 70 ns. While NVC seems to trigger the assert too early.
library ieee;
use ieee.std_logic_1164.all;
entity stable_test is
end entity;
architecture behave of stable_test is
signal test : std_logic := '0';
signal test_stable : boolean := false;
begin
test_stable <= test'stable(50 ns);
process
begin
test <= '0';
wait for 10 ns;
test <= '1';
wait for 10 ns;
test <= '0';
wait for 10 ns;
test <= '0';
for i in 0 to 6 loop
wait for 10 ns;
assert not (test'stable(50 ns)) report "Assert from process!";
end loop;
wait;
end process;
end architecture behave;NVC
nvc 1.15.2 (1.15.2.r0.g2fe12d4f) (Using LLVM 14.0.0)
Copyright (C) 2011-2025 Nick Gasson
This program comes with ABSOLUTELY NO WARRANTY. This is free software, and
you are welcome to redistribute it under certain conditions. See the GNU
General Public Licence for details.
** Error: 40ns+0: Assert from process!
Process :stable_test:_p1 at stable_test.vhd:18
** Error: 50ns+0: Assert from process!
Process :stable_test:_p1 at stable_test.vhd:18
** Error: 60ns+0: Assert from process!
Process :stable_test:_p1 at stable_test.vhd:18
** Error: 70ns+0: Assert from process!
Process :stable_test:_p1 at stable_test.vhd:18
** Error: 80ns+0: Assert from process!
Process :stable_test:_p1 at stable_test.vhd:18
** Error: 90ns+0: Assert from process!
Process :stable_test:_p1 at stable_test.vhd:18
** Error: 100ns+0: Assert from process!
Process :stable_test:_p1 at stable_test.vhd:18GHDL
GHDL 5.0.0-dev (4.1.0.r288.g10fbb188b) [Dunoon edition]
Compiled with GNAT Version: 12.3.0
static elaboration, mcode JIT code generator
Written by Tristan Gingold.
Copyright (C) 2003 - 2024 Tristan Gingold.
GHDL is free software, covered by the GNU General Public License. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
stable_test.vhd:29:7:@70ns:(assertion error): Assert from process!
stable_test.vhd:29:7:@80ns:(assertion error): Assert from process!
stable_test.vhd:29:7:@90ns:(assertion error): Assert from process!
stable_test.vhd:29:7:@100ns:(assertion error): Assert from process!Modelsim
Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
vmap work work
Modifying modelsim.ini
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
Start time: 09:55:39 on Mar 27,2025
vcom -2008 stable_test.vhd
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity stable_test
-- Compiling architecture behave of stable_test
End time: 09:55:39 on Mar 27,2025, Elapsed time: 0:00:00
Errors: 0, Warnings: 0
Reading pref.tcl
# 2020.1
# vsim -c work.stable_test -do "run -all; quit"
# Start time: 09:55:39 on Mar 27,2025
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading work.stable_test(behave)
# run -all
# ** Error: Assert from process!
# Time: 70 ns Iteration: 0 Instance: /stable_test
# ** Error: Assert from process!
# Time: 80 ns Iteration: 0 Instance: /stable_test
# ** Error: Assert from process!
# Time: 90 ns Iteration: 0 Instance: /stable_test
# ** Error: Assert from process!
# Time: 100 ns Iteration: 0 Instance: /stable_test
# quit
# End time: 09:55:39 on Mar 27,2025, Elapsed time: 0:00:00
# Errors: 4, Warnings: 0See https://github.com/ketilroed/stable_test for corresponding wave-diagrams for the test_stable signal.