Definition of signal/constant/type is not allowed to depend on previous defined type #1173
Description
When defining signals, constants or types that depend on a previously defined type, an error message is generated.
In the example below, the type t_test is defined as a record and later the bit width of the t_test.sig_vector is used, which is not allowed in nvc.
library ieee;
use ieee.std_logic_1164.all;
package test_pkg is
type t_test is record
sig : std_logic;
sig_vector : std_logic_vector(15 downto 0);
end record;
constant C_WIDTH : integer := t_test.sig_vector'length;
constant C_CONSTANT : std_logic_vector(t_test.sig_vector'range) := (others => '1');
type t_test_2 is record
sig : std_logic;
sig_vector : std_logic_vector(t_test.sig_vector'range);
end record;
end package;Error message:
** Error: invalid use of type T_TEST
> C:\temp\test_pkg.vhd:11
|
6 | type t_test is record
| ^ T_TEST declared here
...
11 | constant C_WIDTH : integer := t_test.sig_vector'length;
| ^^^^^^ error occurred here
** Error: invalid use of type T_TEST
> C:\temp\test_pkg.vhd:13
|
6 | type t_test is record
| ^ T_TEST declared here
...
13 | constant C_CONSTANT : std_logic_vector(t_test.sig_vector'range) := (others => '1');
| ^^^^^^ error occurred here
** Error: invalid use of type T_TEST
> C:\temp\test_pkg.vhd:17
|
6 | type t_test is record
| ^ T_TEST declared here
...
17 | sig_vector : std_logic_vector(t_test.sig_vector'range);
| ^^^^^^ error occurred here
This code works in Modelsim and Riviera Pro.