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Error: cannot reference signal ... during static elaboration #1144

@pevhall

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@pevhall

I'm getting the following error when trying to move my sim to nvc

** Error: cannot reference signal MSTR_RPLY_O during static elaboration
     > /home/pev.hall/git/PJ005.Emulator.fw/fw/lib/vhdl/ram_iface/ram_iface_split.vhd:117
     |
 117 |   constant RPLY_FLAT_W : natural := get_flat_slv_w(mstr_rply_o);

mstr_rply_o is a port declared like so:

    mstr_rply_o : out ram_iface_rply_t (
      data(DATA_W -1 downto 0)
    );

get_flat_slv_w is a function declared like so

  function get_flat_slv_w(rply : ram_iface_rply_t) return natural is
  begin
    return 2 + rply.data'length;
  end function;

This is preventing me from using a basic coding pattern I use a lot. I'm passing in a signal to functions during elaboration so I can extract information about the signal's type. I use this technique frequently with VHDL2008's unconstrained records. I have tested it on the following simulators and it works:

  • GHDL
  • Vivado ISIM
  • Riveria Pro
    I'd love if I could get this basic coding pattern working on your simulator as well. (I'm hoping to use nvc in earnest with cocotb).

Thank you for your hard work and any assistance you can provide.

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