Fatal: cannot heap allocate r19 on previously working testbench #1029
Description
I'm getting what looks like a regression on a testbench I haven't run in a while, but used to work.
Testbench code is here: https://github.com/oxidecomputer/quartz/tree/main/hdl/ip/vhd/synchronizers/sims
nvc --version
nvc 1.14.0 (1.14.0.r42.gd5e3844b) (Using LLVM 14.0.0) [debug]
Copyright (C) 2011-2024 Nick Gasson
Crash Details:
Name LIB.SYNCHRONIZERS_TB.BENCH
Kind process
Context LIB.SYNCHRONIZERS_TB
Blocks 11
Registers 100
Types 43
VUNIT_LIB.COM_TYPES_PKG.ACTOR_T {-2^31..2^31-1}
Variables 11
RESET_A // $<0..8> => 0..8
RESET_B // $<0..8> => 0..8
BACD1_WRITE // $<0..8> => 0..8
BACD1_LAUNCH_BUS // [*] : $<0..8> => 0..8 => 0..8
BACD1_DATAVALID // $<0..8> => 0..8
BACD1_LATCH_BUS // [*] : $<0..8> => 0..8 => 0..8
TACD_LATCH_OUT // $<0..8> => 0..8
TEST_BYTE // [8] : 0..8 => 0..8
TEST_DATA // [32] : 0..8 => 0..8
GPIO_DATA // [32] : 0..8 => 0..8
MSG_TARGET // VUNIT_LIB.COM_TYPES_PKG.ACTOR_T{}
Begin
0: r0 := debug locus LIB.SYNCHRONIZERS_TB-TB.elab-1217 // D<>
r1 := bind external r0 // $<0..8> => 0..8
RESET_A := store r1
r2 := debug locus LIB.SYNCHRONIZERS_TB-TB.elab-1421 // D<>
r3 := bind external r2 // $<0..8> => 0..8
RESET_B := store r3
r4 := debug locus LIB.SYNCHRONIZERS_TB-TB.elab-1424 // D<>
r5 := bind external r4 // $<0..8> => 0..8
BACD1_WRITE := store r5
r6 := debug locus LIB.SYNCHRONIZERS_TB-TB.elab-1427 // D<>
r7 := bind external r6 // [*] : $<0..8> => 0..8 => 0..8
r8 := const 8 // # => 8
r9 := uarray len r7 dim 0 // #
length check left r8 == right r9 locus r6
r10 := unwrap r7 // $<0..8>
r11 := const 7 // -2^31..2^31-1 => 7
r12 := const 0 // -2^31..2^31-1 => 0
r13 := const 1 // 0..1 => 1
r14 := wrap r10 [r11 r12 r13] // [*] : $<0..8> => 0..8
r15 := debug locus LIB.SYNCHRONIZERS_TB-TB.elab-1238 // D<>
BACD1_LAUNCH_BUS := store r14
r16 := debug locus LIB.SYNCHRONIZERS_TB-TB.elab-1430 // D<>
r17 := bind external r16 // $<0..8> => 0..8
BACD1_DATAVALID := store r17
r18 := debug locus LIB.SYNCHRONIZERS_TB-TB.elab-1433 // D<>
r19 := bind external r18 // [*] : $<0..8> => 0..8 => 0..8
r20 := uarray len r19 dim 0 // #
length check left r8 == right r20 locus r18
r21 := unwrap r19 // $<0..8>
r22 := wrap r21 [r11 r12 r13] // [*] : $<0..8> => 0..8
r23 := debug locus LIB.SYNCHRONIZERS_TB-TB.elab-1250 // D<>
BACD1_LATCH_BUS := store r22
r24 := debug locus LIB.SYNCHRONIZERS_TB-TB.elab-1436 // D<>
r25 := bind external r24 // $<0..8> => 0..8
TACD_LATCH_OUT := store r25
r26 := index TEST_BYTE // @<0..8> => 0..8
r27 := const 2 // 0..8 => 2
r26 := memset r27 length r8
r28 := debug locus LIB.SYNCHRONIZERS_TB-TB+197 // D<>
r29 := const 2147483647 // -2^31..2^31-1 => 2^31-1
r30 := const 0 // 0..1 => 0
r31 := debug locus LIB.SYNCHRONIZERS_TB-TB+178 // D<>
// Elided bounds check for r11
// Elided bounds check for r12
r32 := const 32 // # => 32
r33 := index TEST_DATA // @<0..8> => 0..8
r33 := memset r27 length r32
r34 := debug locus LIB.SYNCHRONIZERS_TB-TB+230 // D<>
r35 := const 31 // -2^31..2^31-1 => 31
r36 := debug locus LIB.SYNCHRONIZERS_TB-TB+211 // D<>
// Elided bounds check for r35
// Elided bounds check for r12
r37 := index GPIO_DATA // @<0..8> => 0..8
r37 := memset r27 length r32
r38 := debug locus LIB.SYNCHRONIZERS_TB-TB+263 // D<>
r39 := debug locus LIB.SYNCHRONIZERS_TB-TB+244 // D<>
// Elided bounds check for r35
// Elided bounds check for r12
r40 := index MSG_TARGET // @<VUNIT_LIB.COM_TYPES_PKG.ACTOR_T{}>
r41 := const {r12} // VUNIT_LIB.COM_TYPES_PKG.ACTOR_T{}
r42 := address of r41 // @<VUNIT_LIB.COM_TYPES_PKG.ACTOR_T{}>
r40 := copy r42
r43 := link package VUNIT_LIB.RUN_PKG // P<VUNIT_LIB.RUN_PKG>
r44 := link var r43 RUNNER // @<$<0..8>> => $<0..8>
r45 := load indirect r44 // $<0..8>
r46 := const 21 // # => 21
drive signal r45 count r46
r47 := link package VUNIT_LIB.COM_PKG // P<VUNIT_LIB.COM_PKG>
r48 := link var r47 NET // @<$<0..8>> => $<0..8>
r49 := load indirect r48 // $<0..8>
r50 := const 5 // # => 5
drive signal r49 count r50
return
1: r51 := link package VUNIT_LIB.RUN_PKG // P<VUNIT_LIB.RUN_PKG>
r52 := link var r51 RUNNER // @<$<0..8>> => $<0..8>
r53 := load indirect r52 // $<0..8>
r54 := debug locus VUNIT_LIB.RUN_PKG+216 // D<>
r55 := const 21 // # => 21
r56 := var upref 1, RUNNER_CFG // @<[*] : 0..255> => 0..255
r57 := load indirect r56 // [*] : 0..255 => 0..255
pcall VUNIT_LIB.RUN_PKG.TEST_RUNNER_SETUP(s37VUNIT_LIB.RUN_TYPES_PKG.RUNNER_SYNC_TS) r51, r53, r57 resume 2
2: resume VUNIT_LIB.RUN_PKG.TEST_RUNNER_SETUP(s37VUNIT_LIB.RUN_TYPES_PKG.RUNNER_SYNC_TS)
r58 := load RESET_B // $<0..8> => 0..8
r59 := const 1 // # => 1
sched event on r58 count r59
wait 3
3: r60 := load RESET_B // $<0..8> => 0..8
r61 := const 1 // # => 1
clear event on r60 count r61
r62 := resolved r60 // @<0..8> => 0..8
r63 := load indirect r62 // 0..8
r64 := const 2 // 0..8 => 2
r65 := cmp r63 == r64
cond r65 then 4 else 5
4: jump 6
5: r66 := load RESET_B // $<0..8> => 0..8
r67 := const 1 // # => 1
sched event on r66 count r67
wait 3
6: r68 := link package VUNIT_LIB.RUN_PKG // P<VUNIT_LIB.RUN_PKG>
r69 := fcall VUNIT_LIB.RUN_PKG.TEST_SUITE()B r68 // 0..1
cond r69 then 7 else 8
7: r70 := link package VUNIT_LIB.RUN_PKG // P<VUNIT_LIB.RUN_PKG>
r71 := const 98 // 0..255 => 98
r72 := const 97 // 0..255 => 97
r73 := const 99 // 0..255 => 99
r74 := const 100 // 0..255 => 100
r75 := const 95 // 0..255 => 95
r76 := const 115 // 0..255 => 115
r77 := const 105 // 0..255 => 105
r78 := const 108 // 0..255 => 108
r79 := const [r71,r72,r73,r74,r75,r71,r72,r76,r77,r73,r75,r72,r78,r77,r72,r76] // [16] : 0..255 => 0..255
r80 := address of r79 // @<0..255> => 0..255
r81 := const 1 // -2^31..2^31-1 => 1
r82 := const 16 // -2^31..2^31-1 => 16
r83 := const 0 // 0..1 => 0
r84 := wrap r80 [r81 r82 r83] // [*] : 0..255
r85 := fcall VUNIT_LIB.RUN_PKG.RUN(S)B r70, r84 // 0..1
cond r85 then 9 else 10
8: Empty basic block
9: r86 := index TEST_BYTE // @<0..8> => 0..8
r87 := const 2 // 0..8 => 2
r88 := const [r87,r87,r87,r87,r87,r87,r87,r87] // [8] : 0..8 => 0..8
r89 := address of r88 // @<0..8> => 0..8
r90 := debug locus LIB.SYNCHRONIZERS_TB-TB+409 // D<>
r91 := const 8 // # => 8
r86 := copy r89 count r91
r92 := link package VUNIT_LIB.CHECK_PKG // P<VUNIT_LIB.CHECK_PKG>
r93 := load BACD1_LATCH_BUS // [*] : $<0..8> => 0..8 => 0..8
r94 := unwrap r93 // $<0..8>
r95 := resolved r94 // @<0..8> => 0..8
r96 := uarray left r93 dim 0 // #
r97 := uarray right r93 dim 0 // #
r98 := uarray dir r93 dim 0 // 0..1
r99 := wrap r95 [r96 r97 r98] // [*] : 0..8 <----
10: Empty basic block
** Fatal: cannot heap allocate r19
[0x5fbe1b6347b8] ../src/diag.c:1052 diag_femit
[0x5fbe1b63499f] ../src/diag.c:1077 diag_emit
[0x5fbe1b54a533] ../src/util.c:585 fatal_trace
[0x5fbe1b60a24c] ../src/vcode.c:516 vcode_heap_allocate
[0x5fbe1b60a01f] ../src/vcode.c:418 vcode_heap_allocate
[0x5fbe1b60a01f] ../src/vcode.c:418 vcode_heap_allocate
[0x5fbe1b60a0bc] ../src/vcode.c:436 vcode_heap_allocate
[0x5fbe1b60a01f] ../src/vcode.c:418 vcode_heap_allocate
[0x5fbe1b60a01f] ../src/vcode.c:418 vcode_heap_allocate
[0x5fbe1b60a01f] ../src/vcode.c:418 vcode_heap_allocate
[0x5fbe1b5efe1f] ../src/lower.c:6469 lower_pcall
[0x5fbe1b5f2d09] ../src/lower.c:7328 lower_stmt
[0x5fbe1b5ef4c9] ../src/lower.c:6277 lower_sequence
[0x5fbe1b5ef671] ../src/lower.c:6313 lower_if
[0x5fbe1b5f2cd9] ../src/lower.c:7321 lower_stmt
[0x5fbe1b5ef4c9] ../src/lower.c:6277 lower_sequence
[0x5fbe1b5f09ba] ../src/lower.c:6683 lower_while
[0x5fbe1b5f2d25] ../src/lower.c:7331 lower_stmt
[0x5fbe1b5ef4c9] ../src/lower.c:6277 lower_sequence
[0x5fbe1b60174f] ../src/lower.c:11497 lower_process
[0x5fbe1b5b8483] ../src/elab.c:2047 elab_process
[0x5fbe1b5b8907] ../src/elab.c:2137 elab_stmts
[0x5fbe1b5b671f] ../src/elab.c:1562 elab_architecture
[0x5fbe1b5b9426] ../src/elab.c:2337 elab
[0x5fbe1b541763] ../src/nvc.c:485 elaborate
[0x5fbe1b545585] ../src/nvc.c:2133 process_command
[0x5fbe1b545ac5] ../src/nvc.c:2293 main