This repository is a fork of rocket-chip. The only difference is added module that contains a single AXI4 memory mapped register TEST_CODE.scala and Node.scala file which is obtained from here. Both files can be found inside /src/main/scala/TEST_HERE directory.
The last rocket-chip commit in which the given code builds is 5571442 (this branch is a fork from this specific commit). The given code on next commit 9a2d27b won't compile. Please see the branch: RegisterRouterError.
In order to start Verilog generation please run the script:
$ ./RUNME.shOr in the command line just type:
$ sbt "runMain axi4test.AXI4TestBlockApp"Please see branch: RegisterRouterError.