I have a problem driving simple Wishbone slave from VUnit WB master. It fails already on the first transaction with message
Error: Pop from empty queue. Waveform of faulty behaviour looks like this:

After a bit of investigating I've found out that error comes this process:
https://github.com/VUnit/vunit/blob/master/vunit/vhdl/verification_components/src/wishbone_master.vhd#L146
which is receiving message sent here:
https://github.com/VUnit/vunit/blob/master/vunit/vhdl/verification_components/src/wishbone_master.vhd#L97

I think that the problem is connected with delta cycles. My WB slave logic looks like this:

ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;

The wb_o.ack and wb_o.stall signals are set in the same delta cycle. But it looks like WB master expects that ack should be set at least one delta cycle later (assuming that I correctly understand how VUnit message passing works).

@slaweksiluk is my reasoning correct?

VUnit 4.4.0
Modelsim SE (Linux) 10.7a