Problem with component binding when using component instantiation #691
Description
Problem description
I am experiencing problems with GHDL not being able to bind components, when component instantiation is used. I need to use component instantiation instead of entity instantiation for my project, as the version of Xilinx unisim library that I am using depends on it. I have created a MWE, below, that demonstrates the problem. The test_component is supposed to count up until it reaches 10, on every clock cycle. When I run my VUnit python script, I get the following warning:
test_tb.vhdl:26:16:warning: instance "test_component_0" of component "test_component" is not bound [-Wbinding]
The simulation then starts, but the check_equality check fails, as the test_component_0 is never correctly instantiated:
1000000000000 fs - check - ERROR - Equality check failed Counter result: - Got -2147483648. Expected 10.
Minimum working example
Code (run.py):
#!/usr/bin/python3
from pathlib import Path
from vunit import VUnit
# Create VUnit instance by parsing command line arguments
project = VUnit.from_argv(vhdl_standard='1993')
flags = ["-frelaxed", "-fexplicit", "--ieee=synopsys", "--warn-default-binding", "--warn-binding", "--warn-library", "--warn-body", "--warn-specs"]
ROOT = Path(__file__).parent
project.add_library('test_lib').add_source_files(ROOT / "test.vhdl")
project.add_library('test_tb').add_source_files(ROOT / "test_tb.vhdl")
project.set_compile_option("ghdl.a_flags", flags)
project.set_sim_option("ghdl.elab_flags", flags)
# Run vunit function
project.main()Code (test.vhdl):
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package test_pkg is
component test_component is
generic(
terminate_at : integer := 10
);
port(
rst : in std_logic;
clk : in std_logic;
done : out std_logic;
counter : out integer
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_component is
generic(
terminate_at : integer := 10
);
port(
rst : in std_logic;
clk : in std_logic;
done : out std_logic;
counter : out integer
);
end test_component;
architecture behav of test_component is
signal counter_sig : integer := 0;
begin
counter <= counter_sig;
process(rst, clk)
begin
if rst = '1' then
counter_sig <= 0;
done <= '0';
else
if rising_edge(clk) then
if counter_sig = terminate_at then
done <= '1';
else
done <= '0';
counter_sig <= counter_sig + 1;
end if;
end if;
end if;
end process;
end architecture;Testbench (tset_tb.vhdl):
library vunit_lib;
--context vunit_lib.vunit_context;
use vunit_lib.run_pkg.all;
use vunit_lib.check_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library test_lib;
use test_lib.test_pkg.all;
entity test_tb is
generic (runner_cfg : string);
end test_tb;
architecture behav of test_tb is
constant clock_frequency : integer := 1000;
constant clock_period : time := 1000 ms / clock_frequency;
signal rst : std_logic;
signal clk : std_logic := '0';
signal done : std_logic;
signal counter : integer;
begin
test_component_0 : test_component
generic map (
terminate_at => 10
)
port map (
rst => rst,
clk => clk,
done => done,
counter => counter
);
-- Generate clock
clk <= not clk after clock_period/2;
main : process
begin
test_runner_setup(runner, runner_cfg);
rst <= '1';
wait for 1 ms;
rst <= '0';
assert false report "Test started!" severity note;
while not done = '1' loop
assert false report "Test not done!" severity note;
wait for 1 ms;
end loop;
assert false report "Test done! " & integer'image(counter) severity note;
check_equal(counter, 10, result("Counter result:"));
test_runner_cleanup(runner);
end process;
end architecture;