In a project I have some test that run 1min in simulation time with signals that needs to be stable this long. For this I use the check_stable() function. The clock of the simulation is 50MHz.
After round about 42s of simulation time the simulation aborts with the following error:

RUNTIME: Fatal Error: RUNTIME_0043 check.vhd (848): Value -2147483648 out of range (0 to 2147483647)

check.vhd line 848

It seams the code uses a clock count which overrun.

The current workaround is to end the first stability check at 30s and start a new one 2 clock cycle later.

Simulator: Aldec Active-HDL 9.2 (sadly i cannot use a newer Version)