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Add readability aliases for Gate.op_param. These aliases assign nam… Run Python tests #144: Commit 137ff35 pushed by fdxmw
August 6, 2025 23:38 1m 25s development
development
August 6, 2025 23:38 1m 25s
Add documentation and examples for Const.val, `Register.reset_value… Run Python tests #143: Commit 0a57cd4 pushed by fdxmw
August 5, 2025 22:44 1m 14s development
development
August 5, 2025 22:44 1m 14s
Fix a typo in CHANGELOG.md's release notes for 0.12. Run Python tests #142: Commit ef456b6 pushed by fdxmw
July 28, 2025 16:58 1m 10s development
development
July 28, 2025 16:58 1m 10s
Run Python tests Run Python tests #141: by fdxmw
July 28, 2025 16:56 1m 12s 0.12
0.12
July 28, 2025 16:56 1m 12s
Update CHANGELOG.md for 0.12 release Run Python tests #140: Commit 5ad9ed6 pushed by fdxmw
July 25, 2025 22:02 1m 18s development
development
July 25, 2025 22:02 1m 18s
Update output_to_verilog to inline temporary wires, using `GateGrap… Run Python tests #139: Commit 98d2b5c pushed by fdxmw
July 25, 2025 21:30 1m 14s development
development
July 25, 2025 21:30 1m 14s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #138: Pull request #471 synchronize by fdxmw
July 25, 2025 20:52 1m 17s fdxmw:verilog
fdxmw:verilog
July 25, 2025 20:52 1m 17s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #137: Pull request #471 synchronize by fdxmw
July 24, 2025 23:54 1m 13s fdxmw:verilog
fdxmw:verilog
July 24, 2025 23:54 1m 13s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #136: Pull request #471 synchronize by fdxmw
July 24, 2025 23:38 1m 13s fdxmw:verilog
fdxmw:verilog
July 24, 2025 23:38 1m 13s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #135: Pull request #471 synchronize by fdxmw
July 24, 2025 22:04 1m 12s fdxmw:verilog
fdxmw:verilog
July 24, 2025 22:04 1m 12s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #134: Pull request #471 synchronize by fdxmw
July 24, 2025 01:51 1m 11s fdxmw:verilog
fdxmw:verilog
July 24, 2025 01:51 1m 11s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #133: Pull request #471 synchronize by fdxmw
July 24, 2025 01:43 1m 13s fdxmw:verilog
fdxmw:verilog
July 24, 2025 01:43 1m 13s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #132: Pull request #471 opened by fdxmw
July 23, 2025 18:49 1m 13s fdxmw:verilog
fdxmw:verilog
July 23, 2025 18:49 1m 13s
Initial implementation of GateGraph, an alternative PyRTL logic rep… Run Python tests #131: Commit 3deeedd pushed by fdxmw
July 22, 2025 18:16 1m 12s development
development
July 22, 2025 18:16 1m 12s
Initial implementation of GateGraph, an alternative PyRTL logic representation Run Python tests #130: Pull request #470 synchronize by fdxmw
July 22, 2025 18:12 1m 16s fdxmw:gate
fdxmw:gate
July 22, 2025 18:12 1m 16s
Initial implementation of GateGraph, an alternative PyRTL logic representation Run Python tests #129: Pull request #470 synchronize by fdxmw
July 21, 2025 23:31 1m 9s fdxmw:gate
fdxmw:gate
July 21, 2025 23:31 1m 9s
Initial implementation of GateGraph, an alternative PyRTL logic representation Run Python tests #128: Pull request #470 synchronize by fdxmw
July 21, 2025 23:21 1m 20s fdxmw:gate
fdxmw:gate
July 21, 2025 23:21 1m 20s
Initial implementation of GateGraph, an alternative PyRTL logic representation Run Python tests #127: Pull request #470 synchronize by fdxmw
July 21, 2025 17:36 1m 15s fdxmw:gate
fdxmw:gate
July 21, 2025 17:36 1m 15s
Initial implementation of GateGraph, an alternative PyRTL logic representation Run Python tests #126: Pull request #470 synchronize by fdxmw
July 19, 2025 01:47 1m 14s fdxmw:gate
fdxmw:gate
July 19, 2025 01:47 1m 14s
Initial implementation of GateGraph, an alternative PyRTL logic representation Run Python tests #125: Pull request #470 synchronize by fdxmw
July 19, 2025 01:28 1m 11s fdxmw:gate
fdxmw:gate
July 19, 2025 01:28 1m 11s
Initial implementation of GateGraph, an alternative PyRTL logic representation Run Python tests #124: Pull request #470 synchronize by fdxmw
July 18, 2025 23:37 1m 18s fdxmw:gate
fdxmw:gate
July 18, 2025 23:37 1m 18s
Initial implementation of GateGraph, an alternative PyRTL logic representation Run Python tests #123: Pull request #470 synchronize by fdxmw
July 18, 2025 23:07 1m 24s fdxmw:gate
fdxmw:gate
July 18, 2025 23:07 1m 24s
Initial implementation of GateGraph, an alternative PyRTL logic representation Run Python tests #122: Pull request #470 opened by fdxmw
July 18, 2025 22:32 1m 12s fdxmw:gate
fdxmw:gate
July 18, 2025 22:32 1m 12s
Simplify Verilog export string formatting code. No functionality chan… Run Python tests #121: Commit 370aa4b pushed by fdxmw
July 10, 2025 04:33 1m 16s development
development
July 10, 2025 04:33 1m 16s
Add a to_ipynb.py script that converts a PyRTL example script to a … Run Python tests #120: Commit 18e0639 pushed by fdxmw
July 9, 2025 22:19 1m 12s development
development
July 9, 2025 22:19 1m 12s