cpu/esp_common: fix unaligned access in periph_flashpage #17150
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gschorcht
reviewed
Nov 7, 2021
cpu/esp_common/periph/flash.c
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| @@ -269,7 +269,7 @@ esp_err_t IRAM_ATTR spi_flash_read(size_t addr, void *buff, size_t size) | |||
| critical_enter(); | |||
| Cache_Read_Disable(PRO_CPU_NUM); | |||
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| result |= esp_rom_spiflash_read (addr, (uint32_t*)_flash_buf, len_full_words); | |||
| result |= esp_rom_spiflash_read (addr, _flash_buf, len_full_words); | |||
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Suggested change
| result |= esp_rom_spiflash_read (addr, _flash_buf, len_full_words); | |
| result |= esp_rom_spiflash_read(addr, _flash_buf, len_full_words); |
|
Works as expected. Tested on |
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gschorcht
approved these changes
Nov 7, 2021
|
Thx! :-) |
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Contribution description
As the title says.
Testing procedure
This should make sure that the buffer never gets allocated at an address not suitable for 32 bit reads / writes, which I believe would have cause hard faults on Xtensa.
Issues/PRs references
Split out of #14955