tests/periph_spi: add support for printing SPI clock rates on stm32 #14768

hugueslarrive · 2020-08-15T14:41:19Z

Contribution description

cmd_init function help show possible speeds for each peripherals and directly store the clk argument in spiconf

Testing procedure

Issues/PRs references

See also #14731.
Depends on PR #14749.

benpicco · 2020-08-15T17:50:43Z

I think #14749 will provide a better solution to this, exposing registers to the API is a bad idea.

hugueslarrive · 2020-08-16T10:57:55Z

Hello @benpicco,

#14749 is a different thing, is it provide a way to set any of the 8 possible values for a device ? Moreover one does not preclude the other.

Why a bad idea ? If you are using this kind of option, one could expect you know what you are doing and it's so simple...

benpicco · 2020-08-16T12:38:04Z

#14749 will let you do spi_acquire(bus, cs, mode, MHZ(54)).
Letting the user set he register directly is a bad idea because it breaks any abstraction and now the SPI driver can't make any assumptions about that register anymore because it's not the sole 'owner' anymore.

If there is a shortcoming in the SPI API / driver we should fix that instead of hacking around it, otherwise we end up with an unmaintainable mess.

benpicco · 2020-09-03T17:23:02Z

#14749 has been merged, can we close this?

hugueslarrive · 2020-09-03T22:30:20Z

Hello @benpicco

Is it currently possible to know the SPI clock speeds actually supported by a specific device with tests/periph_spi?

I think it might be helpful.

Can't you merge it ? Otherwise I can improve it.

benpicco · 2020-09-03T22:38:06Z

Is it currently possible to know the SPI clock speeds actually supported by a specific device with tests/periph_spi?

I'm afraid not

I think it might be helpful.

Yea that would be neat.
Unfortunately I don't think we have an interface for getting that information out of the platform drivers.
Do you have an idea?

Can't you merge it ? Otherwise I can improve it.

Merge what? :D
If you want to extend the test, sure go ahread.
But keep in mind that the tests should be platform independent.

You can add a stm32-specific test though if you so desire.

aabadie · 2020-09-04T06:07:01Z

To print the actual SPI clock you can enable debug output in the spi driver:

RIOT/cpu/stm32/periph/spi.c

Line 36 in ba67f6a

#define ENABLE_DEBUG (0)

The each time the SPI is acquired the clock will be printed in stdout:

RIOT/cpu/stm32/periph/spi.c

Lines 215 to 219 in ba67f6a

    
           DEBUG("[spi] acquire: requested clock: %"PRIu32", resulting clock: %"PRIu32 
        
                 " BR divider: %u\n", 
        
                 clk, 
        
                 periph_apb_clk(spi_config[bus].apbbus)/(1 << (br + 1)), 
        
                 br);

…n stm32

hugueslarrive · 2020-09-06T22:49:45Z

If you want to extend the test, sure go ahread.
But keep in mind that the tests should be platform independent.

Does this mean that I am not allowed to use #ifdef like I did in the main.c of a test ?

You can add a stm32-specific test though if you so desire.

tests/stm32_periph_spi and tests/stm32_periph_spi_dma ? What about code duplication ?

hugueslarrive · 2020-09-06T22:56:41Z

2020-09-07 00:51:58,341 #  init
2020-09-07 00:51:58,345 # usage: init <dev> <mode> <clk> [cs port] [cs pin]
2020-09-07 00:51:58,346 # 	dev:
2020-09-07 00:51:58,347 # 		0: SPI_DEV(0)
2020-09-07 00:51:58,349 # 	mode:
2020-09-07 00:51:58,352 # 		0: POL:0, PHASE:0 - on first rising edge
2020-09-07 00:51:58,356 # 		1: POL:0, PHASE:1 - on second rising edge
2020-09-07 00:51:58,359 # 		2: POL:1, PHASE:0 - on first falling edge
2020-09-07 00:51:58,363 # 		3: POL:1, PHASE:1 - on second falling edge
2020-09-07 00:51:58,364 # 	clk:
2020-09-07 00:51:58,365 # 		0: 100 KHz
2020-09-07 00:51:58,366 # 		1: 400 KHz
2020-09-07 00:51:58,367 # 		2: 1 MHz
2020-09-07 00:51:58,368 # 		3: 5 MHz
2020-09-07 00:51:58,369 # 		4: 10 MHz
2020-09-07 00:51:58,373 # 		SPI_DEV(0), CLOCK_APB2 = 64000000Hz
2020-09-07 00:51:58,375 # 			250000: 64000000/256
2020-09-07 00:51:58,377 # 			500000: 64000000/128
2020-09-07 00:51:58,379 # 			1000000: 64000000/64
2020-09-07 00:51:58,381 # 			2000000: 64000000/32
2020-09-07 00:51:58,383 # 			4000000: 64000000/16
2020-09-07 00:51:58,385 # 			8000000: 64000000/8
2020-09-07 00:51:58,388 # 			16000000: 64000000/4
2020-09-07 00:51:58,390 # 			32000000: 64000000/2
2020-09-07 00:51:58,393 # 			*: other values will be rounded.
2020-09-07 00:51:58,394 # 	cs port:
2020-09-07 00:51:58,398 # 		Port of the CS pin, set to -1 for hardware chip select
2020-09-07 00:51:58,399 # 	cs pin:
2020-09-07 00:51:58,404 # 		Pin used for chip select. If hardware chip select is enabled,
2020-09-07 00:51:58,408 # 		this value specifies the internal HWCS line
init 0 0 4 0 0
2020-09-07 00:52:14,267 #  init 0 0 4 0 0
2020-09-07 00:52:14,273 # SPI_DEV(0) initialized: mode: 0, clk: 4, cs_port: 0, cs_pin: 0
bench
2020-09-07 00:52:20,413 #  bench
2020-09-07 00:52:20,417 # ### Running some benchmarks, all values in [us] ###
2020-09-07 00:52:20,420 # ### Test				Transfer time	user time
2020-09-07 00:52:20,420 # 
2020-09-07 00:52:20,437 #  1 - write 1000 times 1 byte:			13017	13021
2020-09-07 00:52:20,454 #  2 - write 1000 times 2 byte:			12830	12834
2020-09-07 00:52:20,575 #  3 - write 1000 times 100 byte:		116783	14756
2020-09-07 00:52:20,606 #  4 - write 1000 times 1 byte to register:	25782	25787
2020-09-07 00:52:20,636 #  5 - write 1000 times 2 byte to register:	25658	25663
2020-09-07 00:52:20,771 #  6 - write 1000 times 100 byte to register:	129627	27631
2020-09-07 00:52:20,787 #  7 - read 1000 times 2 byte:			12596	12599
2020-09-07 00:52:20,908 #  8 - read 1000 times 100 byte:		116564	14569
2020-09-07 00:52:20,938 #  9 - read 1000 times 2 byte from register:	25408	25412
2020-09-07 00:52:21,072 # 10 - read 1000 times 100 byte from register:	129408	27381
2020-09-07 00:52:21,089 # 11 - transfer 1000 times 2 byte:		12595	12600
2020-09-07 00:52:21,210 # 12 - transfer 1000 times 100 byte:		116596	14569
2020-09-07 00:52:21,241 # 13 - transfer 1000 times 2 byte to register:	25502	25506
2020-09-07 00:52:21,375 # 14 - transfer 1000 times 100 byte to register:129533	27506
2020-09-07 00:52:21,396 # 15 - acquire/release 1000 times:		16767	16772
2020-09-07 00:52:22,398 # -- - SUM:					908666	296606
2020-09-07 00:52:22,398 # 
2020-09-07 00:52:22,401 # ### All runs complete ###
init 0 0 8000000 0 0
2020-09-07 00:52:33,800 #  init 0 0 8000000 0 0
2020-09-07 00:52:33,806 # SPI_DEV(0) initialized: mode: 0, clk: 8000000, cs_port: 0, cs_pin: 0
bench
2020-09-07 00:52:36,312 #  bench
2020-09-07 00:52:36,317 # ### Running some benchmarks, all values in [us] ###
2020-09-07 00:52:36,320 # ### Test				Transfer time	user time
2020-09-07 00:52:36,321 # 
2020-09-07 00:52:36,337 #  1 - write 1000 times 1 byte:			13017	13022
2020-09-07 00:52:36,354 #  2 - write 1000 times 2 byte:			12830	12834
2020-09-07 00:52:36,474 #  3 - write 1000 times 100 byte:		116783	14756
2020-09-07 00:52:36,505 #  4 - write 1000 times 1 byte to register:	25783	25787
2020-09-07 00:52:36,536 #  5 - write 1000 times 2 byte to register:	25658	25662
2020-09-07 00:52:36,670 #  6 - write 1000 times 100 byte to register:	129627	27630
2020-09-07 00:52:36,687 #  7 - read 1000 times 2 byte:			12595	12599
2020-09-07 00:52:36,807 #  8 - read 1000 times 100 byte:		116564	14568
2020-09-07 00:52:36,838 #  9 - read 1000 times 2 byte from register:	25408	25413
2020-09-07 00:52:36,972 # 10 - read 1000 times 100 byte from register:	129408	27382
2020-09-07 00:52:36,989 # 11 - transfer 1000 times 2 byte:		12595	12600
2020-09-07 00:52:37,110 # 12 - transfer 1000 times 100 byte:		116595	14567
2020-09-07 00:52:37,140 # 13 - transfer 1000 times 2 byte to register:	25502	25505
2020-09-07 00:52:37,275 # 14 - transfer 1000 times 100 byte to register:129533	27507
2020-09-07 00:52:37,296 # 15 - acquire/release 1000 times:		16768	16771
2020-09-07 00:52:38,298 # -- - SUM:					908666	296603
2020-09-07 00:52:38,299 # 
2020-09-07 00:52:38,301 # ### All runs complete ###
init 0 0 16000000 0 0
2020-09-07 00:52:47,306 #  init 0 0 16000000 0 0
2020-09-07 00:52:47,312 # SPI_DEV(0) initialized: mode: 0, clk: 16000000, cs_port: 0, cs_pin: 0
bench
2020-09-07 00:52:49,547 #  bench
2020-09-07 00:52:49,552 # ### Running some benchmarks, all values in [us] ###
2020-09-07 00:52:49,555 # ### Test				Transfer time	user time
2020-09-07 00:52:49,555 # 
2020-09-07 00:52:49,572 #  1 - write 1000 times 1 byte:			13017	13022
2020-09-07 00:52:49,589 #  2 - write 1000 times 2 byte:			12814	12819
2020-09-07 00:52:49,659 #  3 - write 1000 times 100 byte:		66283	14724
2020-09-07 00:52:49,690 #  4 - write 1000 times 1 byte to register:	25783	25787
2020-09-07 00:52:49,721 #  5 - write 1000 times 2 byte to register:	25642	25647
2020-09-07 00:52:49,805 #  6 - write 1000 times 100 byte to register:	79158	27600
2020-09-07 00:52:49,822 #  7 - read 1000 times 2 byte:			12580	12584
2020-09-07 00:52:49,892 #  8 - read 1000 times 100 byte:		66064	14505
2020-09-07 00:52:49,922 #  9 - read 1000 times 2 byte from register:	25392	25397
2020-09-07 00:52:50,006 # 10 - read 1000 times 100 byte from register:	78908	27351
2020-09-07 00:52:50,022 # 11 - transfer 1000 times 2 byte:		12580	12584
2020-09-07 00:52:50,093 # 12 - transfer 1000 times 100 byte:		66095	14538
2020-09-07 00:52:50,124 # 13 - transfer 1000 times 2 byte to register:	25486	25490
2020-09-07 00:52:50,209 # 14 - transfer 1000 times 100 byte to register:79033	27479
2020-09-07 00:52:50,229 # 15 - acquire/release 1000 times:		16767	16772
2020-09-07 00:52:51,231 # -- - SUM:					605602	296299
2020-09-07 00:52:51,231 # 
2020-09-07 00:52:51,233 # ### All runs complete ###
init 0 0 32000000 0 0
2020-09-07 00:53:32,713 #  init 0 0 32000000 0 0
2020-09-07 00:53:32,719 # SPI_DEV(0) initialized: mode: 0, clk: 32000000, cs_port: 0, cs_pin: 0
bench
2020-09-07 00:53:35,580 #  bench
2020-09-07 00:53:35,585 # ### Running some benchmarks, all values in [us] ###
2020-09-07 00:53:35,587 # ### Test				Transfer time	user time
2020-09-07 00:53:35,587 # 
2020-09-07 00:53:35,604 #  1 - write 1000 times 1 byte:			13017	13021
2020-09-07 00:53:35,621 #  2 - write 1000 times 2 byte:			12814	12818
2020-09-07 00:53:35,667 #  3 - write 1000 times 100 byte:		42283	14787
2020-09-07 00:53:35,698 #  4 - write 1000 times 1 byte to register:	25782	25787
2020-09-07 00:53:35,728 #  5 - write 1000 times 2 byte to register:	25642	25646
2020-09-07 00:53:35,789 #  6 - write 1000 times 100 byte to register:	55126	27631
2020-09-07 00:53:35,805 #  7 - read 1000 times 2 byte:			12580	12584
2020-09-07 00:53:35,851 #  8 - read 1000 times 100 byte:		42064	14572
2020-09-07 00:53:35,881 #  9 - read 1000 times 2 byte from register:	25392	25396
2020-09-07 00:53:35,941 # 10 - read 1000 times 100 byte from register:	54908	27381
2020-09-07 00:53:35,958 # 11 - transfer 1000 times 2 byte:		12579	12584
2020-09-07 00:53:36,004 # 12 - transfer 1000 times 100 byte:		42096	14599
2020-09-07 00:53:36,035 # 13 - transfer 1000 times 2 byte to register:	25486	25490
2020-09-07 00:53:36,095 # 14 - transfer 1000 times 100 byte to register:55033	27502
2020-09-07 00:53:36,116 # 15 - acquire/release 1000 times:		16767	16772
2020-09-07 00:53:37,118 # -- - SUM:					461569	296570
2020-09-07 00:53:37,118 # 
2020-09-07 00:53:37,121 # ### All runs complete ###
init 0 0 50000000 0 0
2020-09-07 00:53:51,736 #  init 0 0 50000000 0 0
2020-09-07 00:53:51,743 # SPI_DEV(0) initialized: mode: 0, clk: 50000000, cs_port: 0, cs_pin: 0
bench
2020-09-07 00:53:54,265 #  bench
2020-09-07 00:53:54,269 # ### Running some benchmarks, all values in [us] ###
2020-09-07 00:53:54,272 # ### Test				Transfer time	user time
2020-09-07 00:53:54,273 # 
2020-09-07 00:53:54,289 #  1 - write 1000 times 1 byte:			13017	13021
2020-09-07 00:53:54,306 #  2 - write 1000 times 2 byte:			12814	12818
2020-09-07 00:53:54,352 #  3 - write 1000 times 100 byte:		42283	14788
2020-09-07 00:53:54,383 #  4 - write 1000 times 1 byte to register:	25782	25787
2020-09-07 00:53:54,414 #  5 - write 1000 times 2 byte to register:	25642	25646
2020-09-07 00:53:54,474 #  6 - write 1000 times 100 byte to register:	55126	27631
2020-09-07 00:53:54,490 #  7 - read 1000 times 2 byte:			12580	12584
2020-09-07 00:53:54,536 #  8 - read 1000 times 100 byte:		42064	14572
2020-09-07 00:53:54,566 #  9 - read 1000 times 2 byte from register:	25392	25397
2020-09-07 00:53:54,626 # 10 - read 1000 times 100 byte from register:	54908	27381
2020-09-07 00:53:54,643 # 11 - transfer 1000 times 2 byte:		12579	12584
2020-09-07 00:53:54,689 # 12 - transfer 1000 times 100 byte:		42096	14598
2020-09-07 00:53:54,720 # 13 - transfer 1000 times 2 byte to register:	25486	25490
2020-09-07 00:53:54,780 # 14 - transfer 1000 times 100 byte to register:55033	27503
2020-09-07 00:53:54,801 # 15 - acquire/release 1000 times:		16767	16772
2020-09-07 00:53:55,803 # -- - SUM:					461569	296572
2020-09-07 00:53:55,803 # 
2020-09-07 00:53:55,806 # ### All runs complete ###

tests/periph_spi/main.c

stale · 2021-06-02T16:37:15Z

This issue has been automatically marked as stale because it has not had recent activity. It will be closed if no further activity occurs. If you want me to ignore this issue, please mark it with the "State: don't stale" label. Thank you for your contributions.

hugueslarrive requested a review from MrKevinWeiss as a code owner August 15, 2020 14:41

hugueslarrive changed the title ~~cpu/stm32/periph/spi: Added an option to bypass spi_divtable limitations at build time~~ tests/periph_spi: adaptation for #14749 Aug 17, 2020

hugueslarrive force-pushed the spi_use_raw_br branch 3 times, most recently from ab3f51e to 0785249 Compare August 20, 2020 12:38

benpicco requested a review from bergzand August 20, 2020 13:08

hugueslarrive changed the title ~~tests/periph_spi: adaptation for #14749~~ tests/periph_spi: tests/periph_spi: add support for arbitrary SPI clock rates setting on stm32 Aug 20, 2020

hugueslarrive changed the title ~~tests/periph_spi: tests/periph_spi: add support for arbitrary SPI clock rates setting on stm32~~ tests/periph_spi: add support for arbitrary SPI clock rates setting on stm32 Aug 27, 2020

hugueslarrive force-pushed the spi_use_raw_br branch from 0785249 to b54627f Compare September 6, 2020 20:08

tests/periph_spi: add support for arbitrary SPI clock rates setting o…

a916cd7

…n stm32

hugueslarrive force-pushed the spi_use_raw_br branch from b54627f to a916cd7 Compare September 6, 2020 22:29

benpicco changed the title ~~tests/periph_spi: add support for arbitrary SPI clock rates setting on stm32~~ tests/periph_spi: add support for printing SPI clock rates setting on stm32 Sep 6, 2020

benpicco requested a review from aabadie September 6, 2020 23:07

benpicco changed the title ~~tests/periph_spi: add support for printing SPI clock rates setting on stm32~~ tests/periph_spi: add support for printing SPI clock rates on stm32 Sep 6, 2020

benpicco reviewed Sep 6, 2020

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tests/periph_spi: add support for printing SPI clock rates

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benpicco added Area: tests Area: tests and testing framework Type: enhancement The issue suggests enhanceable parts / The PR enhances parts of the codebase / documentation labels Sep 9, 2020

stale bot added the State: stale State: The issue / PR has no activity for >185 days label Jun 2, 2021

stale bot closed this Jul 8, 2021

hugueslarrive deleted the spi_use_raw_br branch August 12, 2021 22:15

hugueslarrive mentioned this pull request Aug 13, 2021

periph/spi: add support for printing and testing SPI clock rate #16727

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Contribution description

Testing procedure

Issues/PRs references

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