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Description
Description
The code from the current master
branch (exact commit later) hang during initialization of ADC, for example tests/periph/adc
.
I observe this behavior using nucleo-l476rg
and nucleo-l496zg
.
Steps to reproduce the issue
Flash mentioned boards (or maybe other from L4xxx family) using tests/periph/adc
and observe console.
Expected results
The working code should prints new measurements each 100 ms:
main(): This is RIOT! (Version: 2021.07-devel-8076-gd8bd2-HEAD)
RIOT ADC peripheral driver test
This test will sample all available ADC lines once every 100ms with
a 10-bit resolution and print the sampled results to STDIO
Successfully initialized ADC_LINE(0)
Successfully initialized ADC_LINE(1)
Successfully initialized ADC_LINE(2)
Successfully initialized ADC_LINE(3)
Successfully initialized ADC_LINE(4)
Successfully initialized ADC_LINE(5)
Successfully initialized ADC_LINE(6)
ADC_LINE(0): 317
ADC_LINE(1): 296
ADC_LINE(2): 340
ADC_LINE(3): 287
ADC_LINE(4): 214
ADC_LINE(5): 228
ADC_LINE(6): 152
ADC_LINE(0): 196
ADC_LINE(1): 232
. . .
Actual results
Using current master
branch after connection program hangs, presenting after reset only this output:
main(): This is RIOT! (Version: 2021.07-devel-10796-g216435)
RIOT ADC peripheral driver test
This test will sample all available ADC lines once every 100ms with
a 10-bit resolution and print the sampled results to STDIO
Versions
This behavior was introduced by the commit 6247b2aea4b3ab20b29f7f6da903f57bb84f4ffa.
The code from the preceding commit 4b4d77a0fe6c57f64e30a5b852e0eea2c72f87d8 works.
I could fix this issue using dirty hack with defines:
#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L496ZG)
//old clock configuration code
#else
//new clock configuration code
#endif
... but maybe there is a better solution.
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