Fix classical bit mapping in HLS pass #14597
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Co-authored-by: Alexander Ivrii <alexi@il.ibm.com>
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Pull Request Test Coverage Report for Build 15686757882Warning: This coverage report may be inaccurate.This pull request's base commit is no longer the HEAD commit of its target branch. This means it includes changes from outside the original pull request, including, potentially, unrelated coverage changes.
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mtreinish
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Jun 16, 2025
Previously the cargs were being written to a Vec<usize> as an intermediate storage, however we are just returning them directly and don't need to allocate or change the types. This commit just works with the slice returned from the interner directly which both simplifies the code and should also be faster.
mtreinish
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Jun 16, 2025
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@Mergifyio backport stable/2.0 |
✅ Backports have been created
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* Map classical bits from block to outer circuit Co-authored-by: Alexander Ivrii <alexi@il.ibm.com> * Add regression test * Add reno * Avoid allocating cargs Previously the cargs were being written to a Vec<usize> as an intermediate storage, however we are just returning them directly and don't need to allocate or change the types. This commit just works with the slice returned from the interner directly which both simplifies the code and should also be faster. --------- Co-authored-by: Alexander Ivrii <alexi@il.ibm.com> Co-authored-by: Matthew Treinish <mtreinish@kortar.org> (cherry picked from commit 9ec464a)
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* Map classical bits from block to outer circuit Co-authored-by: Alexander Ivrii <alexi@il.ibm.com> * Add regression test * Add reno * Avoid allocating cargs Previously the cargs were being written to a Vec<usize> as an intermediate storage, however we are just returning them directly and don't need to allocate or change the types. This commit just works with the slice returned from the interner directly which both simplifies the code and should also be faster. --------- Co-authored-by: Alexander Ivrii <alexi@il.ibm.com> Co-authored-by: Matthew Treinish <mtreinish@kortar.org> (cherry picked from commit 9ec464a)
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* Map classical bits from block to outer circuit * Add regression test * Add reno * Avoid allocating cargs Previously the cargs were being written to a Vec<usize> as an intermediate storage, however we are just returning them directly and don't need to allocate or change the types. This commit just works with the slice returned from the interner directly which both simplifies the code and should also be faster. --------- (cherry picked from commit 9ec464a) Co-authored-by: Elena Peña Tapia <57907331+ElePT@users.noreply.github.com> Co-authored-by: Alexander Ivrii <alexi@il.ibm.com> Co-authored-by: Matthew Treinish <mtreinish@kortar.org>
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* Map classical bits from block to outer circuit * Add regression test * Add reno * Avoid allocating cargs Previously the cargs were being written to a Vec<usize> as an intermediate storage, however we are just returning them directly and don't need to allocate or change the types. This commit just works with the slice returned from the interner directly which both simplifies the code and should also be faster. --------- (cherry picked from commit 9ec464a) Co-authored-by: Elena Peña Tapia <57907331+ElePT@users.noreply.github.com> Co-authored-by: Alexander Ivrii <alexi@il.ibm.com> Co-authored-by: Matthew Treinish <mtreinish@kortar.org>
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Summary
This PR fixes a bug in HLS where classical registers were mapped to the indices in within the high level object they were defined on, instead of the corresponding index in the global circuit.
Fixes #14569 .
Details and comments
The bug was introduced in 2.0, so the fix should be backported to the
stable/2.0branch, but notstable/1.4.