Add the gates ECR, iSwap, CY, SX, SXdg, DCX to the Clifford class (backport #9623) #9640
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) * add SX and SXdg gates * add CY, iSwap and ECR gates * add new gates to the Clifford docs * improve ECR * add more tests for the new gates * add ECR decomposition into Clifford gates to the equivalence library * update ECR in equivalence library * add DCX to clifford_circuits.py * add test for dcx * add release notes * more efficient synthesis of an ECR gate * change the release notes from features to bug fix --------- Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 9128ebd)
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jakelishman
approved these changes
Feb 22, 2023
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This is an automatic backport of pull request #9623 done by Mergify.
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