Fix DenseLayout when loose bits are present in input circuit #8843
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This commit fixes the DenseLayout transpiler pass to correctly handle when an input circuit contains loose bits. Previously the pass would incorrectly assume there was always a register in the circuit and only construct the output layout with registers. This caused the pass to return an empty layout if there were no quantum registers present in the circuit, even if there were qubits in the circuit. This commit fixes this by creating the layout per qubit and then only adding the registers as metadata to the layout after the fact.
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| for qreg in dag.qregs.values(): | ||
| for i in range(qreg.size): | ||
| layout[qreg[i]] = int(best_sub[map_iter]) | ||
| map_iter += 1 | ||
| layout.add_register(qreg) |
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I don't even know why Layout tracks registers, but it does seem to be part of the interface, so best to keep it. I'm guessing it's from before, when registers owned qubits.
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Yeah, neither am I, and tbh I don't think it is 100% needed here anymore as without this all the tests passed, but I kept it in just in case there was something I wasn't considering.
Pull Request Test Coverage Report for Build 3199091475
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Summary
This commit fixes the DenseLayout transpiler pass to correctly handle when an input circuit contains loose bits. Previously the pass would incorrectly assume there was always a register in the circuit and only construct the output layout with registers. This caused the pass to return an empty layout if there were no quantum registers present in the circuit, even if there were qubits in the circuit. This commit fixes this by creating the layout per qubit and then only adding the registers as metadata to the layout after the fact.
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