Skip to content

Performance regression with optional registers #5868

@mtreinish

Description

@mtreinish

Information

  • Qiskit Terra version: Master since: 9040bb9c
  • Python version: Any
  • Operating system: Any

What is the current behavior?

Since #5486 merged there has been a performance regression across the board with everything that operates on bits and/or registers in qiskit. For example:

https://qiskit.github.io/qiskit/#converters.ConverterBenchmarks.time_dag_to_circuit?machine=dedicated-benchmarking-softlayer-baremetal&os=Linux%204.15.0-46-generic&ram=16GB&p-n_qubits=8&p-depth=128&commits=9040bb9c

or

https://qiskit.github.io/qiskit/#transpiler_levels.TranspilerLevelBenchmarks.time_quantum_volume_transpile_50_x_20?machine=dedicated-benchmarking-softlayer-baremetal&os=Linux%204.15.0-46-generic&ram=16GB&p-transpiler%20optimization%20level=0&commits=9040bb9c

My guess is that this is around the changes made in Register.__eq__ in #5486 but haven't profiled it to confirm.

The hope is that the remaining patches in the optional registers patch series will address the performance impact: https://github.com/Qiskit/qiskit-terra/pulls?q=is%3Apr+is%3Aopen+label%3Aoptional-registers This issue is so we continue to track the regression as a release blocker to ensure we confirm the performance regression is addressed before we release with the code.

Metadata

Metadata

Assignees

Type

No type

Projects

No projects

Milestone

No milestone

Relationships

None yet

Development

No branches or pull requests

Issue actions