Control flow mpl visualization not respecting layout #10601
Description
Environment
- Qiskit Terra version: 0.25.0
- Python version: 3.11
- Operating system: Linux
What is happening?
When running the matplotlib based circuit visualization with a transpiled circuit that is using control flow. The new control flow visualization support is drawing the gates on the incorrect qubit. It looks like it's not doing the control flow block qubit mapping correctly to factor in the layout. This results in the gates inside a control flow block ending up outside the box drawn for the control flow block.
For example:
How can we reproduce the issue?
from qiskit.circuit import QuantumCircuit, QuantumRegister, ClassicalRegister
from qiskit.compiler import transpile
from qiskit.providers.fake_provider import FakeBelemV2
from qiskit.circuit import SwitchCaseOp
qreg = QuantumRegister(2)
creg = ClassicalRegister(2)
qc = QuantumCircuit(qreg, creg)
qc.h([0, 1])
qc.h([0, 1])
qc.h([0, 1])
qc.measure([0, 1], [0, 1])
with qc.switch(creg) as case:
with case(0): # if the register is '00'
qc.z(0)
with case(1, 2): # if the register is '01' or '10'
qc.cx(0, 1)
with case(case.DEFAULT): # the default case
qc.h(0)
backend = FakeBelemV2()
backend.target.add_instruction(SwitchCaseOp, name="switch_case")
transpile(qc, backend, optimization_level=2, seed_transpiler=671_42).draw('mpl')What should happen?
The gates on the right end of the circuit on ancilla_0 should be on q2_1 (and the cx should be shifted down by one row) in the same position.
Any suggestions?
No response