What should we add?

VF2PostLayout has a strict_direction mode which is designed to run after physical optimization to use the final gates on each qubit for estimating the error rates, instead of just avg gate errors with estimated gate counts. The pass ensures that all circuit gates are supported on the target when considering an alternative layout, so it's safe to run at the end of transpilation. Right now we don't run it in this mode in the default pipeline because we found experimentally that using the average gate error mode with undirected graphs occasionally provided better results because of the extra freedom to flip a 2q gate (you can see discussion of this in the paper).

However now that we've sped up the transpiler significantly nd increased what optimization level 2 runs the difference between level 2 and 3 is pretty small. We can leverage this strict mode for VF2PostLayout to add an additional differentiating factor to level 3. Level 3 is defined as spending extra time for optimization that aren't necessarily guaranteed to improve output quality, running VF2PostLayout a second time in strict mode at the end of the optimization stage fits this criteria and there is little harm in doing it for optimization level 3.