This project is an implementation of a FPGA accelrated Deep learning engine to run Deep learning models.

The FPGA board chosen for this project is the TUL PYNQ-Z2 Development Board,

The Board features the ZYNQ XC7Z020-1CLG400C SOC with

• 650MHz dual-core Cortex-A9 processor

• DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports

• 13,300 logic slices, each with four 6-input LUTs and 8 flip-flops

• 630 KB of fast block RAM

• 220 DSP slices

• 512MB DDR3 memory

• DPU ip block design implementation
• DPU synthesis and Bitstream generation
• DPU sd card image using Petalinux
• DL classifier training and quantization
• DNNDK Optimization of DL model
• Deployment on PYNQ-Z2

Xilinx Vivado 2020.1

DNNDK

MobaXterm