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@standardgalactic
Cogito Ergo Sum standardgalactic
   Standard Galactic Alphabet

Xanadu Canada

@sirnails
Dave sirnails

Birmingham, UK

@maleiter
Markus Leiter maleiter

P2L2 GmbH Hagenberg im Mühlkreis, Austria

@MJoergen
Michael Jørgensen MJoergen
Experienced software and firmware developer. Primary focus is with embedded applications in telecommunications, see my LinkedIn profile.

Weibel Scientific Denmark

@MortenZilmer
Morten Zilmer MortenZilmer
Electronics engineer engaged in embedded equipment development using FPGA/ASIC and related technologies.

Copenhagen, Denmark

@stnolting
stnolting
Roads? Where we're going we don't need roads. - "Doc" Emmett L. Brown

@fraunhofer-ims 🇪🇺 European Union

@BMaheshwari
Bhagesh C. Maheshwari BMaheshwari
ASIC Design Engineer | Former Intern in CERN | Former Cultural Ambassador of Pakistan in USA | Gold Medalist

Xilinx Inc. Dublin Ireland

@embed-me
embed-me embed-me
Embedded Systems Engineering, Reverse Engineering and Hacking

embed-me

@matzesc
Mathias Schmalisch matzesc
FPGA Design, Digital Signal Processing, Wireless Communications, Cryptography, Embedded Systems, Linux, Windows, Emacs

Virginia, USA

@euripedesrocha
Euripedes euripedesrocha

@espressif Czech Republic

@Ahmad-Zaklouta
Ahmad Zaklouta Ahmad-Zaklouta
Interested in FPGA, VHDL, C programming, and ARM

Synective Labs Stockholm

@umarcor
Unai Martinez-Corral umarcor

UPV/EHU Bilbo, Bizkaia, Euskadi, Spain, Europe

@mitoksim
Timothy mitoksim
Engineering Profesional

California

@lukipedio
Luca Colombini lukipedio
Senior design engineer @ CAEN

CAEN S.p.A. Italy

@kammoh
Kamyar Mohajerani kammoh
PhD student at George Mason University and member of Cryptographic Engineering Research Group

@GMUCERG Fairfax, VA

@benreynwar
Ben Reynwar benreynwar

USC, Information Sciences Institiute Tucson, Arizona, USA

@tmeissner
T. Meissner tmeissner
FPGA-Engineer doing design and verification using VHDL, SystemVerilog, SVA and PSL.

Dresden, Germany

@muscoder
Mustafa Tosun muscoder

Ozyegin University Istanbul/TURKEY

@mariuselv
mariuselv mariuselv
VHDL, Python, UVVM

Bitvis / Inventas Norway

@shravan-shandilya
Shravan Shandilya shravan-shandilya
A generalist who can become a specialist in logarithmic time

Bangalore

@Paebbels
Patrick Lehmann Paebbels
Vice-Chair of the IEEE P1076 Working Group (VHDL Analysis and Standardization Group- VASG). I'm a VHDL expert and FPGA-technology trainer at @PLC2.

@PLC2 Bötzingen, Germany