Yup,

I think most of the interest for X-pessimism is due to the assumption that "GLS can be only ran late in the design process". I think it is much better to move GLS sooner into the design process. Just having fast synthesis flow with dummy synthesis that is constrained only with basic clocks. On zero-delay netlist, all of the X-prop / sim - syn mismatch can be easily caught.

X tracing is super useful when debugging GLS. I have used it succesfully in Cadence SimVision. Now that I use DVE, it is less practical, but I guess that is because DVE is more than 10 years obsolete SW. I bet this will have amazing experience with Verdi.

I also try to minimize Xs in the design, but sometimes to reduce area, we use non-reset flops. We do zero delay GLS on full set of all tests (including IP level as well as chip top level) to catch these issues. So this is more-of an "out of interest" question.

I don't know how plausible is to add it to NVC, AFAIK this would need good GUI debugger and maybe Schematic tracer.